AR# 34009

描述

解决方案

ML605 boards with Virtex-6 FPGA CES (Engineering Sample) siliconmust use the v1.3 rev 2 Integrated Block Wrapper for PCI Express available in ISE 12.1and later software versions. The rev 2 patch is available from (Xilinx Answer 36552) and fixes issues with linking up and implementation.

Later versions of the Integrated Block Wrapper for PCI Express (v1.4 and later) only work on Virtex-6 FPGA Production grade silicon and can be used on ML605 boards that have production silicon. For more information about the Integrated Block Wrapper for PCI Express releases, see the Release Notes found in the IP Release Notes Guide (XTP025): http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

To identify if your ML605 board has CES or Production silicon, use iMPACT to read the IDCODE back of the silicon and you should see one of the following:

iMPACT output fromCES Silicon

'2': IDCODE is '24250093' (in hex).
'2': : Manufacturer's ID = Xilinx xc6vlx240t, Version : 2

iMPACT output fromProduction Silicon

'2': IDCODE is '44250093' (in hex).
'2': : Manufacturer's ID = Xilinx xc6vlx240t, Version : 4

For more information, see (Xilinx Answer 34033) and theVirtex-6 FPGA errata found in the Virtex-6 Documentation Center: http://www.xilinx.com/support/documentation/virtex-6.htm#131587


Revision History
01/18/2012 - Updated; added reference to 45723
02/04/2011 - Updated title and content
06/08/2010 - Added information about Answer Record 36008
12/21/2009 - Initial Release

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

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