2. 技术支持
  3. AR# 34115: Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - WARNING:Xst:2016 - Found a loop when searching source

AR# 34115

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Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - WARNING:Xst:2016 - Found a loop when searching source

描述

Synthesizing the Endpoint Block Pus Wrapper for PCI Express gives the following warning message:

WARNING:Xst:2016 - Found a loop when searching source clock on port 'u_pcie_phy_top/u_pcie_gt_v6fxt_1lane/pcie_gt_i/gtx_v6_i/GTXD[0].GTX:TXOUTCLK'

Can this warning message be ignored?

解决方案

The above warning message is incorrectly reported by the XST. It will be corrected in a future release. This warning message can be safely ignored.

Revision History
04/23/2010 - Updated for ISE 12.1 and core version v1.5
03/23/2010 - Initial Release

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
35322 Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A
AR# 34115
日期 05/19/2012
状态 Active
Type 已知问题
器件
Tools
IP
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