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  3. AR# 34285: MIG Design Assistant - Virtex-6 Synthesis and Implementation

AR# 34285

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MIG Design Assistant - Virtex-6 Synthesis and Implementation

描述

This section of the MIG Design Assistant focuses on Synthesis and Implementation of the Virtex-6 DDR3/DDR2 designs. Please select from the below options to find information related to your specific question.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

Usage

The generated MIG Virtex-6 design includes a script file (ise_flow.bat) in the output 'example_design/par' and 'user_design/par' directories. This is the recommended flow for implementing a MIG design. The script file sets all appropriate implementation options (ie - XST, MAP, PAR options) to run the design through the tools.

A create_ise.bat script file is also provided in the output 'example_design/par' and 'user_design/par' directories. This can be used to generate an .ise project file with all MIG rtl/UCF files added and implementation options set appropriately. For ISE users, this file should be run to create the .ise project after which the user logic should be added.

Errors

General error analysis:

  • When errors are seen during synthesis, verify any modifications to the output RTL or the core's instantiation into the user design.
  • When errors are seen during NGDBuild, verify any modifications to the output constraints in the UCF. All of the constraints provided with the MIG core are required. The only changes should be to include the paths from the user design into the MIG constraints.
  • When errors are seen during MAP/PAR, most often pin-outs, general MIG constraints, or rtl parameters that define placement have been modified. To verify any changes, please see the Pin-Out/Banking section of this MIG Design Assistant
For additional information on Synthesis and Implementation Debugging Steps for MIG Virtex-6 DDR3/DDR2 design, please see:


链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
34882 MIG Design Assistant - Virtex-6 Synthesis and Implementation Debug Guide N/A N/A
34266 Xilinx Virtex-6 MIG Solution Center - Design Assistant N/A N/A
AR# 34285
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less
IP
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