AR# 34882

This section of the MIG Design Assistant focuses on Synthesis and Implementation of the Virtex-6 DDR3/DDR2 designs. Below you will find information related to your specific question.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

For a complete list of Synthesis and Implementation debugging for Virtex-6 DDR3/DDR2 designs, please refer to the "Debugging Virtex-6 FPGA DDR2/DDR3 SDRAM Designs"=>"Synthesis and Implementation Debug" section of UG406:

http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf