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  3. AR# 34371: MIG 7 Series and Virtex-6 DDR2/DDR3 Solution Center - Design Assistant - Auto-Refresh Counter (Refresh Period)

AR# 34371

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MIG 7 Series and Virtex-6 DDR2/DDR3 Solution Center - Design Assistant - Auto-Refresh Counter (Refresh Period)

描述

This section of the MIG Design Assistant focuses on refresh, defined by the JEDEC Specification as it applies to the MIG 7 Series and Virtex-6 DDR3/DDR2 designs.

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

The MIG controller is set up by default to automatically send a refresh command every 7.8 microseconds. This auto-generated refresh adheres to the JEDEC specification. An internal counter is used for the auto-refresh period and is set by the TREFI parameter. When the counter expires, the refresh is automatically sent.

Changing the Auto-Refresh Period

MIG does not support turning auto-refresh off. However, it is possible to change the period between refresh commands. The parameter for the refresh period is TREFI.

By default, TREFI is 7.8 microseconds;depending on the temperature you are running the memory, you might want to change this setting. The allowable range for the refresh rate is 3.9 to 7.8 microseconds.

NOTE: Using the Create Custom Part feature, available in the MIG tool, allows the refresh period (trefi - average periodic refresh interval) to be defined within the tool and the corresponding MIG parameters to be set properly.

Manually Sending Refresh

The MIG design includes the ability to manually send a refresh command. The signal app_ref_req, not pulled out to the top level of the user interface, can be used to manually request a refresh. This signal is located in the mem_intfc.v/.vhd module.Asserting this signal tells the memory controller to send out a refresh command. When the refresh is sent, the counter (set through the TREFI parameter) is reset.

It is recommended that users let the controller send these commands at regular intervals to ensure the JEDEC refresh requirements are met, but this signal can be used when needed.

Postponing and Pulling-in Refresh

(Xilinx Answer 42309) Virtex-6 and 7 Series DDR3 - Postponing and Pulling-in REFRESH commands

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
51684 MIG 7 系列 DDR2/DDR3 - JEDEC 规范 N/A N/A
34243 Xilinx Memory Interface Solution Center N/A N/A

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
42309 MIG 7 系列和 Virtex-6 DDR2/DDR3 解决方案中心 - 设计助手 - 推迟执行和拉入 REFRESH 命令 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
42309 MIG 7 系列和 Virtex-6 DDR2/DDR3 解决方案中心 - 设计助手 - 推迟执行和拉入 REFRESH 命令 N/A N/A
34906 MIG 7 Series and Virtex-6 DDR2/DDR3 Solution Center Design Assistant - Controller Responsibilities N/A N/A
34330 MIG Virtex-6 DDR2/DDR3 - JEDEC Specification N/A N/A
AR# 34371
日期 09/18/2012
状态 Active
Type 解决方案中心
器件 More Less
IP
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