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  3. AR# 3447: MAP FATAL ERROR: Illegal situation for H1 pack.
  4. AR# 34477: MIG Virtex-6 DDR2/DDR3 - Capture Logic Placement Requirements

AR# 34477

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MIG Virtex-6 DDR2/DDR3 - Capture Logic Placement Requirements

描述

The MIG Virtex-6 DDR2/DDR3 design uses an internally generated clock to capture the data on DQ during reads. In previous MIG designs (i.e., Virtex-5 DDR2), the DQS strobe was used to capture data. Capturing data with an internally generated clock is beneficial because it is a true free-running clock and has no pre-/post-amble glitches as DQS does. The MIG Virtex-6 FPGA design uses two clocks in the data capture of a DQS byte:
  • Capture Clock
  • Resynchronization Clock
This article addresses the architectural and placement requirements for the capture logic.

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

Placement:
  • One capture clock is used per DQS byte group.
  • Each capture clock requires an OSERDES/IODELAY and BUFIO for each DQS byte group.
  • In order to use these IODELAY and BUFIO elements, a Clock Capable (CCIO) site must be prohibited and logic within the prohibited site locked for capture logic usage.

Constraints:
The MIG output locks the required number of CCIO pins and associated IODELAY and OSERDES sites for the interface generated. These LOCs are contained in the output User Constraints File (design.ucf). Following is an example for a single DQS byte groups capture logic placement:

CONFIG PROHIBIT = E39;
INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt"
LOC = "OLOGIC_X1Y183";
INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_odelay_cpt"
LOC = "IODELAY_X1Y183";

By default, MIG uses Single Region Clock Capable I/O (SRCCIO) sites because all of the related logic data group logic exists within the same bank. Multi-Region CCIO sites can also be used. If it is desired to move the Capture Logic prohibits and site LOCs, users should modify the sites within the output UCF and run the updated UCF through the Verify UCF and Update UCF and Design tool. For more information, see (Xilinx Answer 34386).

Related Information
The design uses an internally generated capture clock, for details see:
(Xilinx Answer 35112) - Internally Generated Capture Clock

While the design does not capture data using DQS, it does monitor the phase of DQS during reads to account for any phase shift due to voltage/temperature changes. If the phase varies, the capture clock phase is adjusted using the MMCM Phase Shift.
(Xilinx Answer 34480) - MIG Virtex-6 DDR2/DDR3 - Phase Detector Circuit and Periodic Reads

Because DQS is not used to capture data, it only needs to be placed on a p/n I/O pair rather then a Clock Capable I/O (CCIO) pair.
(Xilinx Answer 34543) - MIG Virtex-6 DDR2/DDR3 - DQS I/O Placement

For more information on the resynchronization logic, see:
(Xilinx Answer 34540) - MIG Virtex-6 DDR2/DDR3 - Resynchronization Logic Usage and Placement

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
35113 MIG Virtex-6 DDR2/DDR3 PHY - Usage of DQS N/A N/A
35112 MIG Virtex-6 DDR2/DDR3 PHY - Capture Clock N/A N/A
34543 MIG Virtex-6 DDR2/DDR3 - DQS I/O Placement N/A N/A
34540 MIG Virtex-6 DDR2/DDR3 - Resynchronization (RSYNC) logic usage and placement N/A N/A
34386 MIG 7 Series and Virtex-6 DDR2/DDR3 - Verify UCF and Update Design and UCF N/A N/A
34308 MIG Virtex-6 DDR3/DDR2 - Verify pin-out/banking requirements are met N/A N/A
AR# 34477
日期 12/15/2012
状态 Active
Type 综合文章
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