The MIG Virtex-6 DDR2/DDR3 design uses an internally generated clock to capture the data on DQ during reads. In previous MIG designs (i.e.,Virtex-5 DDR2), the DQS strobe was used to capture data. Capturing data with an internally generated clock is beneficial because it is a true free-running clock and has no pre-/post-amble glitches as DQS does.
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The DQS from the memory is not directly used to capture the corresponding read data. Read data is captured using an internally generated capture clock. However, the phase of DQS is monitored in the phase detection circuitry during reads and compared to the capture clock. As their phases vary with changing environmental conditions, the capture clock phase is adjusted. For information on the phase detector circuit, see (Xilinx Answer 34480).
In previous architectures, the DQS signal was required to be on a clock capable IO (CCIO), this is not a requirement for Virtex-6, for details see (Xilinx Answer 34543)
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 34477 | MIG Virtex-6 DDR2/DDR3 - Capture Logic Placement Requirements | N/A | N/A |
| 34543 | MIG Virtex-6 DDR2/DDR3 - DQS I/O Placement | N/A | N/A |