DDR3 SDRAM modules have adopted Fly-by Topology on clocks, address, commands, and control signals to improve signal integrity.
Specifically, the clocks, address, and control signals are all routed in a daisy-chained fashion, and termination is located at the end of each trace.
However, this causes a skew between the strobe (DQS) and the clock (CK) at each memory device on the module.
Write leveling is a new feature in DDR3 SDRAMs which allows the controller to adjust each write DQS independently with respect to the CK forwarded to the DDR3 SDRAM device.
This compensates for the skew between DQS and CK and meets the tDQSS specification.
Since the MIG Virtex-6 and 7 Series DDR3 design uses write leveling for all outputs (single component, multi-component, and DIMM), it is required that the board be laid out using Fly-by Topology on the clock, address, and control lines.
This is documented in the DDR2 and DDR3 SDRAM Memory Interface Solution > Design Guidelines > DDR3 SDRAM > DDR3 Component PCB Routing section of the Virtex-6 Memory Interface Solutions User Guide and in the 7 Series FPGAs Memory Interface Solutions User Guide.
Fly-By Topology is new to DDR3, therefore, this is only a MIG requirement for DDR3.
DDR2 designs should be laid out using T-Branch Topology.
The MIG design will only turn write leveling on for DDR3 designs.
Write Leveling is turned on with the top-level rtl parameter WRLVL (WRLVL="ON").
For more information on the Write Leveling feature and its usage within the MIG Virtex-6 DDR3 design, see the following:
Revision History
08/24/2012 - Added 7 Series information
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 34544 | MIG Virtex-6 DDR2/DDR3 - Board Layout | N/A | N/A |
| 51475 | MIG 7 系列设计助手 - MIG 7 系列 DDR2/DDR3、电路板布局和设计指南 | N/A | N/A |
| 35094 | MIG Virtex-6 and 7 Series DDR3 - Write Leveling | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 35094 | MIG Virtex-6 and 7 Series DDR3 - Write Leveling | N/A | N/A |