AR# 35094

描述

Write Leveling is a DDR3 SDRAM feature that is used to compensate for DQS/CK skew. DDR3 DIMM and multi-component designs must use fly-by topology routing on clocks, address, commands, and control signals. This improves SI, but causes skew between DQS and CK. Write Leveling compensates for this skew.

NOTE: This answer record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

During Write Leveling, CK and DQS are driven by the FPGA while DQ is feedback by the DDR3 SDRAM device to provide feedback.The FPGA then delays DQS using IODELAY taps (Virtex-6 DDR3) or Phaser_OUT taps (7 Series DDR3) until a 0-to-1 transition is detected on DQ.This compensates for DQS/CK skew and ensures the tDQSS specification is met.

Write Leveling is performed immediately after the memory initialization is completed. The MIG Virtex-6and 7 Series DDR3designs perform Write Leveling for ALL DDR3 designs regardless of whether there is one component, multiple components, or a DIMM. This is enabled in the MIG design through the WRLVL parameter in the top-most level rtl file:

parameter WRLVL = "ON",

Virtex-6 Specific Information
Since Write Leveling is performed for all MIG DDR3 designs, there is no need to specify a trace matching requirement between DQS and CK. The design will always calibrate CK-DQS timing.

For detailed information on Write Leveling, refer to:

• DDR2/DDR3 SDRAM Memory Interface Solution > Core Architecture > PHY section of UG406
• Section 4.8 of the DDR3 SDRAM Standard - JEDEC79-3

• For information on other calibration stages, please see (Xilinx Answer 34740).
• For information on Fly-By Routing, please see (Xilinx Answer 34557).
• For information on debugging calibration errors/failures, please see (Xilinx Answer 34743).

7 Series Specific Information
The CK/CK# signals must arrive at each memory device after the DQS/DQS# signals. The recommended value for additional propagation delay on CK/CK# traces relative to DQS/DQS# at each memory device is documented in the Design Guidelines section of UG586.

For detailed information on Write Leveling, refer to:

• DDR2/DDR3 SDRAM Memory Interface Solution > Core Architecture > PHY section of UG586.
• Section 4.8 of the DDR3 SDRAM Standard - JEDEC79-3.

• For information on other calibration stages and debugging calibration errors/failure, please see (Xilinx Answer 43879).
• For information on Fly-By Routing, please see (Xilinx Answer 34557).

Revision History
08/24/12 - Added 7 Series Information

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