2. 技术支持
  3. AR# 3461: M1.4 PAR - PAR runs out of memory during placement of design with hard macros (.nmc's) that contain routing information.
  4. AR# 34612: Virtex-6 FPGA Integrated Endpoint Block v1.4 for PCI Express : Simulation failure when using ISE 11.5 to simulate a v1.4 core generated in ISE Design Suite 11.4

AR# 34612

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Virtex-6 FPGA Integrated Endpoint Block v1.4 for PCI Express : Simulation failure when using ISE 11.5 to simulate a v1.4 core generated in ISE Design Suite 11.4

描述

When usingISE 11.5 to simulate a v1.4 wrapper generated in ISE 11.4, simulation will fail with the following error message:

Attribute Syntax Error : The calculation of VCO frequency=500.000000 Mhz. This exceeds the permitted VCO frequency range of 600.000000 Mhz to 1600.000000 Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN1_PERIOD). Please adjust the attributes to the permitted VCO frequency range.

解决方案

Xilinx recommends regenerating the core using ISE 11.5. This will generate v1.4 rev 2 of the core in which this problem will be fixed.

Revision History

03/08/2010 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
33763 Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.4 and 11.5 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
33763 Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.4 and 11.5 N/A N/A
AR# 34612
日期 05/22/2012
状态 Active
Type 已知问题
器件
IP
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