AR# 35110

描述

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

Write Calibration aligns an entire DQS group to the correct CK clock cycles. This compensates for PCB trace delays and I/O buffer delays that exceed a CK cycle. To perform calibration, clock cycles of delay are added until the desired data pattern is read back. At this time, the correct number of cycles has been determined and write calibration completes. Write Calibration is performed on a per-byte basis.

Write Calibration is performed simultaneously with Read Leveling Stage 2. During this period, multiple writes and reads using the same data pattern (FF00AA5555AA9966) are performed to align write calibration and read calibration properly.The writes are shifted while on the read side bitslip and alignment occurs for different bytes.

Additional Information:

• For detailed information on Write Calibration, please see the DDR2/DDR3 SDRAM Memory Interface Solution > Core Architecture > PHY section of UG406.
• For information on other calibration stages, please see (Xilinx Answer 34740)
• For information on debugging calibration errors/failures, please see (Xilinx Answer 34743)

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