AR# 35218

描述

The MIG 7 Series and Virtex-6 DDR2/DDR3 design includes two output directories containing rtl, the Example Design and the User Design. The Example Design includes sample logic to drive the user interface. This is called the Traffic Generator. The design sends sample writes, reads back the data, and compares the data to ensure accuracy. The design can be configured to send different types of data patterns to test for different types of problems. This Answer Record focuses on the Traffic Generator available with the MIG 7 Series and Virtex-6 DDR2/DDR3 Example Designs.

Note: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

Xilinx recommends first running the Example Design in hardware to confirm there are no board or pin-out related issues. If the MIG design is used without modification and the provided PCB Layout Guidelines are followed, no issues should be seen in hardware with the Example Design. For additional information, see the following Answer Records:

• MIG Virtex-6
• (Xilinx Answer 34308) Pin-Out and Banking Requirements
• (Xilinx Answer 34544) Board Layout Requirements
• MIG 7 Series
• (Xilinx Answer 51317) Pin-Out and Banking Requirements
• (Xilinx Answer 51475) Board Layout Requirements

The Traffic Generator, by default, sends an address as a data pattern. However, the design can be configured to send many different types of data patterns like a Hammer pattern to test for SSO or a PRBS pattern. For full details on the Traffic Generator and available data patterns, see the DDR2/DDR3 SDRAM Memory Interface Solution > Getting Started > Quick Start Example Design section of the Virtex-6 Memory Interface User Guideor the 7 Series FPGAs Memory Interface User Guide. This section also explains how to change the data pattern for simulation or using the ChipScope tool in hardware with the Debug Port.

For information on the MIG Virtex-6 Debug Port, see (Xilinx Answer 35206).
For information on the MIG 7 Series Debug Port and how to debug calibration failures and data errors using the traffic generator, see (Xilinx Answer 43879).

• BEGIN_ADDRESS
• END_ADDRESS
• PRBS_SADDR_MASK_POS
• PRBS_EADDR_MASK_POS

The BEGIN/END_ADDRESS parameters define the address space to be tested. The PRBS_S/EADDR_MASK_POS parameters are used to mask off any bits that are outside the address range. Any bits above or below your defined address range should be masked off using the PRBS parameter. Following is example:

localparam C4_p0_BEGIN_ADDRESS = 32'h00000400;
localparam C4_p0_END_ADDRESS = 32'h000007ff;
localparam C4_p0_PRBS_EADDR_MASK_POS = 32'hfffff800;
localparam C4_p0_PRBS_SADDR_MASK_POS = 32'h00000400;

链接问答记录

主要问答记录

相关答复记录