AR# 34319

描述

The 7 series and Virtex-6 MIG DDR2/DDR3 designs are generated with two output designs, the User Design and the Example Design. The User Design should be included in the overall system. The Example Design should be used for a general understanding of the IP, simulation, and debug. This section of the MIG Design Assistant focuses on the MIG generated Example Design.

Note: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

The MIG generated Example Design includes a synthesizable testbench to generate various traffic data patterns to the memory controller that are fully verified in simulation and hardware. This synthesizable testbench is called the Traffic Generator. The example design can be used to observe the behavior of the MIG design both in simulation and hardware. It is also a powerful aid in identifying design and board related problems. Verifying a proper simulation environment and a working board with the example design should be starting points in your design flow.

For a complete description on the Example Design's usage, please refer to the "DDR2 and DDR3 SDRAM Memory Interface Solution" => "Getting Started" => "Quick Start Example Design" and the"DDR2 and DDR3 SDRAM Memory Interface Solution" => "Core Architecture"sections in the following user guides:

Virtex-6 Memory Interface Solutions User Guide
Series FPGAs Memory Interface Solutions User Guide

(Xilinx Answer 35218) - Traffic Generator Details and Usage

链接问答记录

主要问答记录

子答复记录

相关答复记录