2. 技术支持
  3. AR# 3525: M1.4 Map - 5200: Map is not trimming global reset signals
  4. AR# 35252: MIG v3.0-3.4 Virtex-6 DDR3 - REFCLK Frequency (IODELAYCTRL Reference clock) must be 300 MHz for interfaces running between 480-533 MHz

AR# 35252

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MIG v3.0-3.4 Virtex-6 DDR3 - REFCLK Frequency (IODELAYCTRL Reference clock) must be 300 MHz for interfaces running between 480-533 MHz

描述

The MIG design for Virtex-6 FPGA DDR3 always sets the REFCLK frequency to 200 MHz.

However, for DDR3 interfaces running between 480 - 533 MHz, the REFCLK needs to run at 300 MHz.

Starting with MIG v3.5 (available with ISE 12.2), MIG will properly set the REFCLK frequency to 300 MHz.

In the meantime, manual modifications must be made for designs running in this frequency range.

This answer record details the required changes.

Please note this clock is referred to as the IODELAY reference clock in User Guide 406.

解决方案

Step 1 The MIG top-level rtl includes a REFCLK_PERIOD parameter that is defined as follows:


parameter REFCLK_FREQ = 200,
// # = 200 when design frequency <= 533 MHz,
// = 300 when design frequency > 533 MHz.

This parameter needs to be modified, as follows, to 300 for DDR3 designs running between 480-533 MHz.

parameter REFCLK_FREQ = 300,
// # = 200 when design frequency < 480 MHz,
// = 300 when design frequency >= 480 MHz

Step 2

For designs with existing boards, an MMCM needs to be added to the design to multiply the 200 MHz clock up to 300 MHz to then drive the MIG REFCLK clock.

Ensure CLKFBOUT_MULT_F values of 2, 3, and 4 are not used in this MMCM. 

See (Xilinx Answer 33849) for more information.

For designs without existing boards, simply choose a 300 MHz clock for the MIG REFCLK input.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
34587 MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
34587 MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A
AR# 35252
日期 08/18/2014
状态 Active
Type 已知问题
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