(Xilinx Answer 36195) MIG v3.4 Virtex-6 DDR2 - Unroute errors occur on dqs_p_iodelay due to Map option
Virtex-6 FPGA QDRII+ SRAM (Xilinx Answer 33289) MIG v3.1, v3.2, v3.3, v3.4 Virtex-6 FPGA QDRII+ - Changes required to Samsung simulation model for proper operation and completion of calibration
Spartan-6 FPGA MCB (Xilinx Answer 35978) MIG Spartan-6 MCB - Last word of read burst fails in hardware - bitstream update required for all MCB designs
(Xilinx Answer 35976) MIG Spartan-6 MCB - Design does not come out of reset and requires power-cycle to regain functionality - SW / IP update required
(Xilinx Answer 35818) Spartan-6 FPGA - Memory Controller Block (MCB) Performance Change for DDR2 and DDR3 interfaces
(Xilinx Answer 35044) 11.5/12.1 Spartan-6 Place - The clock placer is not accounting for the proper PLL_ADV to BUFFPLL_MCB connection in larger devices - Results in MIG/MPMC MCB Calibration Failures in Hardware
(Xilinx Answer 35499) MIG v3.4 Spartan-6 Traffic Generator - 128-bit Bi-Directional Port Example Design does not work in hardware
(Xilinx Answer 35250) MIG Spartan-6 MCB - MIG generated ise_flow.bat script file produces error during XST on Windows
(Xilinx Answer 35238) MIG v3.4 Spartan-6 MCB LPDDR - MIG generated ise_flow.bat script file is missing BitGen command to create a bit file
(Xilinx Answer 35245) MIG Spartan-6 MCB - User Interface cannot send commands until calibration completes (cal_done asserts)
(Xilinx Answer 34055) MIG Spartan-6 FPGA MCB - What are the requirements for the RZQ and ZIO pins?
(Xilinx Answer 34089) MIG Spartan-6 FPGA MCB - Some bits of the MCB address bus (mcbx_dram_addr) may violate the input hold time (tIH) specification of the memory device
(Xilinx Answer 34046) MIG v3.3/v3.4, Spartan-6 LPDDR - Calibrated and Un-Calibrated Input Termination features not supported
(Xilinx Answer 35289) MIG v3.4, Spartan-6 FPGA LPDDR - When running the LPDDR design the traffic generator stops sending commands after long write bursts.
(Xilinx Answer 35290) MIG v3.4, Spartan-6L - Error when using Synplify Pro as a synthesis tool and targeting low power Spartan-6 devices
(Xilinx Answer 35485) MIG Spartan-6 - DDR2 - When using Synplify Pro for synthesis the design fails to send data in hardware.
(Xilinx Answer 35057) MIG v3.4, v3.4 - Spartan-6 - The MCB appears to violate the DDR2 Initialization Sequence
(Xilinx Answer 35869) MIG v3.4 - Spartan-6 - When simulating the example design with ModelSim PE I get an "Iteration limit" error.
Virtex-5 FPGA Designs
(Xilinx Answer 35248) MIG v3.4 Virtex-5 FPGA - All VHDL Example Design outputs using Synplify flow will fail in hardware
(Xilinx Answer 36335) MIG v3.3, v3.4 Virtex-5 DDR2 - Data corruption occurs at the beginning or end of a read burst
Virtex-4 FPGA Designs
(Xilinx Answer 35291) MIG v3.4 - Virtex-4 - RLDRAMII - During simulation of the VHDL design iteration limit error occurs
MIG Tool
(Xilinx Answer 35247) MIG v3.4 Virtex-6 DDR2/DDR3 - Fixed Pin-Out tool does not allow selection of VREF sites