AR# 36932: 12.1 EDK - My EDK simulations are not working
AR# 36932
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12.1 EDK - My EDK simulations are not working
描述
When I run through a simulation for my PowerPC embedded project, the software never gets past the initialization of the processor. Why does this occur?
解决方案
This problemoccurs mainly with PowerPC simulations, but the potential is also there for MicroBlaze. In the case of the PowerPC simulation, the processor continues to pre-fetch instructions when not needed.Not all contents in the block RAM are initialized with the processor data which means that the processor can step into a memory location that is empty.By default, the block RAM Unisim model takes on the default VHDL initialization which is 'U'.The processor model goes into an unknown state when it starts reading 'U' values.
To work around thisissue,manually modify the Unisim and Simprim block RAM models found in the following locations:
VHDL: C:\Xilinx\12.1\ISE_DS\ISE\vhdl\src\unisims\primitive\ARAMB36_INTERNAL.vhd -- lines 835 C:\Xilinx\12.1\ISE_DS\ISE\vhdl\src\simprims\primitive\mti\X_ARAMB36_INTERNAL.vhd -- line 845 C:\Xilinx\12.1\ISE_DS\ISE\vhdl\src\simprims\primitive\other\X_ARAMB36_INTERNAL.vhd -- line 845
Modelsim To get the newly changed primitive into your ModelSim library, use the following command at the VSIM prompt: vcom -work unisim C:/Xilinx/12.2/ISE_DS/ISE/vhdl/src/unisims/primitive/ARAMB36_INTERNAL.vhd A similar commandmustbe used for the simprim models as well.
ISim To get the newly changed primitive into your ISim library, open an ISE Design Suite prompt and run the following command: compxlib.exe -s xil_isim -lib unisim -l vhdl -dir C:\Xilinx\12.2\ISE_DS\ISE\vhdl\hdp\[nt|nt64|lin|lin64] A similar command must be used for the simprim models as well.
Verilog: C:\Xilinx\12.2\ISE_DS\ISE\verilog\src\unisims\ARAMB36_INTERNAL.v -- Lines 410 and 648 C:\Xilinx\12.2\ISE_DS\ISE\verilog\src\simprims\X_ARAMB36_INTERNAL.v -- Lines 407 and 1707
Line 410(unisims), 407(simprims):
From: integer count1, countp1, i, i1, i_p, i_mem, init_offset, initp_offset;
To: integer count1, countp1, i, i1, j, j1, i_p, i_mem, init_offset, initp_offset;
Line 648 (unisims), 1707(simprims)
Insert: for (j = 0; j < mem_depth; j = j + 1) begin for (j1 = 0; j1 < widest_width; j1 = j1 + 1) begin tmp_mem[j][j1] = 1'b0; end end
Modelsim To get the newly changed primitive into your ModelSim library, use the following command at the VSIM prompt: vlog -work unisims_ver C:\Xilinx\12.2\ISE_DS\ISE\verilog\src\unisims\ARAMB36_INTERNAL.v A similar commandmustbe used for the simprim models as well.
ISim To get the newly changed primitive into your ISim library, use the following command: compxlib.exe -s xil_isim -lib unisim -l verilog -dir C:\Xilinx\12.2\ISE_DS\ISE\verilog\hdp\[nt|nt64|lin|lin64] A similar command will have to be used for the simprim models as well. This problem is scheduled to be fixed in ISE Design Suite 12.3. For other potential simulation issues, refer to (Xilinx Answer 36026)