This section of the MIG Design Assistant focuses on Core Functionality for the Spartan-6 MCBdesigns. Please select from the below options to find information related to your specific question.
Note:This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 43321 | MIG Spartan-6 MCB - User Interface | N/A | N/A |
| 43319 | MIG Spartan-6 MCB - Clocking and Reset | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 40683 | MIG Spartan-6 MCB - PHY Architecture | N/A | N/A |
| 40532 | MIG Spartan-6 MCB - FPGA Device support | N/A | N/A |
| 40156 | MIG Spartan-6 MCB - Performance | N/A | N/A |
| 40155 | MIG Design Assistant - Spartan-6 MCB Supported Features | N/A | N/A |
| 34204 | MIG v3.0-3.3, Virtex-6 DDR3/DDR2 - Read Leveling Stage 2 fails in hardware due to OCB Monitor issue | N/A | N/A |
| 35976 | MIG、MPMC 和 Spartan-6 MCB 的设计咨询 - 设计不是通过复位产生的，需要重新上电才能恢复功能性（需要软件/IP 核升级） | N/A | N/A |
| 35818 | Design Advisory for Spartan-6 FPGA - Memory Controller Block (MCB) Performance Change for DDR2 Interfaces | N/A | N/A |
| 36291 | MIG, MPMC, Spartan-6 MCB - 在初始配置时出现存储器故障 | N/A | N/A |
| 39076 | MIG Virtex-6, Spartan-6 FPGA MCB - Disabling the DLL from a Micron memory DIMM | N/A | N/A |
| 40876 | MIG 7 Series v1.1 DDR3 SDRAM - MIG allows setting memory frequencies above data sheet specifications | N/A | N/A |
| 41752 | MIG 7 Series DDR3/DDR2 - Can a x16 interface fit into a single bank? | N/A | N/A |
| 37496 | Xilinx Spartan-6 MIG Solution Center - Design Assistant | N/A | N/A |
| AR# 37498 | |
|---|---|
| 日期 | 12/15/2012 |
| 状态 | Active |
| Type | 综合文章 |
| 器件 | |
| IP | |