Version Found: v2.1, v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 45723).
A TIG constraint and optional block RAM pipelining can be added to ease x8 Gen 2 timing closure.
Add the following constraints to the UCF file:
PIN "core/pcie_clocking_i/GEN2_LINK.pipe_clk_bufgmux.CE0" TIG;
PIN "core/pcie_clocking_i/GEN2_LINK.pipe_clk_bufgmux.CE1" TIG;
Also, enabling pipeline registers on the read and write side of the Transaction Block RAM can help timing closure.
To do this, on page 10 of the CORE Generator Customization GUI, select the option for "Buffer Write and Read".
Pipeline Registers for Transaction Block RAM Buffers = Buffer Write and Read.
Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 45723 | Virtex-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface Versions | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 40446 | Virtex-6 FPGA Integrated Block Wrapper v1.7 for PCI Express - Release Notes and Known Issues | N/A | N/A |
| 39353 | Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.2 | N/A | N/A |
| 37937 | Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.1 | N/A | N/A |
| 37936 | Virtex-6 FPGA Integrated Block Wrapper v1.6 for PCI Express - Release Notes and Known Issues | N/A | N/A |