AR# 3924: SYNPLIFY - How do I instantiate an FMAP or HMAP (RLOC) in the HDL code?
AR# 3924
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SYNPLIFY - How do I instantiate an FMAP or HMAP (RLOC) in the HDL code?
描述
Keywords: Verilog, VHDL, Synplify, FMAP, HMAP
Urgency: Standard
General Description: How do I instantiate an FMAP or HMAP in the HDL code?
解决方案
1
This requires user familiarity with the Xilinx device architecture; also, Synplicity does not fully document this feature.
Synplify does not support direct instantiation of FMAP/HMAP in the Verilog/VHDL code. However, Synplicity will be supporting a mechanism in which an user can specify the FMAP/HMAP into which the LUT logic of a particular piece of logic can go through the "xc_map" meta-comment.
The "xc_map" attribute is placed on a module or a VHDL architecture. The contents must be simple logic equations with a single output. The "xc_map" can have the value "hmap" or "fmap". In the 5200 series parts, the FMAP can have up to 5 inputs.
This is not supported in Virtex. Users should contact Synplicity for details.
Version 3.0c1 supports this; however, it has not been fully documented, as it has not yet been completely tested.
2
module fmap_xor4 (z, a, b, c, d); /* synthesis xc_map=fmap */ output z; input a, b, c, d;
assign z = a ^ b ^ c ^ d;
endmodule
module hmap_xor3 (z, a, b, c); /* synthesis xc_map=hmap */ output z; input a, b, c;
entity fmap_xor4 is port ( a, b, c, d : in std_logic; z : out std_logic); end fmap_xor4; architecture rtl of fmap_xor4 is attribute xc_map : STRING; attribute xc_map of rtl : architecture is "fmap";
begin
z <= a xor b xor c xor d;
end rtl;
library IEEE; use IEEE.std_logic_1164.all;
entity hmap_xor3 is port ( a, b, c : in std_logic; z : out std_logic); end hmap_xor3; architecture rtl of hmap_xor3 is attribute xc_map : STRING; attribute xc_map of rtl : architecture is "hmap";
begin
z <= a xor b xor c;
end rtl;
library IEEE; use IEEE.std_logic_1164.all;
entity clb_xor9 is port ( a : in std_logic_vector(8 downto 0); z : out std_logic ); end clb_xor9;
architecture rtl of clb_xor9 is
signal z03, z47 : std_logic;
component hmap_xor3 port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic ); end component;
component fmap_xor4 port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; z : out std_logic ); end component; attribute xc_uset : string; attribute xc_rloc : string; attribute xc_uset of x03 : label is "SET1"; attribute xc_rloc of x03 : label is "R0C0.f"; attribute xc_uset of x47 : label is "SET1"; attribute xc_rloc of x47 : label is "R0C0.g"; attribute xc_uset of zz : label is "SET1"; attribute xc_rloc of zz : label is "R0C0.h";
begin
x03 : fmap_xor4 port map(a(0), a(1), a(2), a(3), z03); x47 : fmap_xor4 port map(a(4), a(5), a(6), a(7), z47); zz : hmap_xor3 port map(z03, z47, a(8), z);
end rtl;
library IEEE; use IEEE.std_logic_1164.all;
entity xor9top is port ( a : in std_logic_vector(8 downto 0); z : out std_logic ); end xor9top;
architecture rtl of xor9top is
component clb_xor9 port ( a : in std_logic_vector (8 downto 0); z : out std_logic); end component;