2. 技术支持
  3. AR# 39549: MIG Virtex-6 DDR2/DDR3 - Read and Write FIFO Depths

AR# 39549

|

MIG Virtex-6 DDR2/DDR3 - Read and Write FIFO Depths

描述

What is the depth of the read and write FIFOs for the core? I want to do a streaming design and would like to know how much is available.

解决方案

The RTL actually instantiates RAM32M instead of FIFOs to store data. Looking at the RTL, the depth of the RAM is 32 bits, but only 4 of the 5 bits are used for addressing.You can see where the RAM are instantiated and how the address lines going to the RAM (e.g., ADDRB) are 4 bits long, so the depth is 16 bits.

Example_design\rtl\ui\ui_wr_data.v

Lines 397-435

// Instantiate pointer RAM. Made up of RAM32M in single write, two read // port mode, 2 bit wide mode.
input [3:0] ram_init_addr;
output wire [3:0] wr_data_buf_addr;
localparam PNTR_RAM_CNT = 2;
generate begin : pointer_ram
wire pointer_we = new_rd_data || ~ram_init_done_r;
wire [3:0] pointer_wr_data = ram_init_done_r
? wr_data_addr_r
: ram_init_addr;
wire [3:0] pointer_wr_addr = ram_init_done_r
? rd_data_indx_r
: ram_init_addr;
genvar i;
for (i=0; i<PNTR_RAM_CNT; i=i+1) begin : rams
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(),
.DOB(wr_data_buf_addr[i*2+:2]),
.DOC(wr_data_pntr[i*2+:2]),
.DOD(),
.DIA(2'b0),
.DIB(pointer_wr_data[i*2+:2]),
.DIC(pointer_wr_data[i*2+:2]),
.DID(2'b0),
.ADDRA(5'b0),
.ADDRB({1'b0, data_buf_addr_cnt_r}),
.ADDRC({1'b0, wr_data_indx_r}),
.ADDRD({1'b0, pointer_wr_addr}),
.WE(pointer_we),
.WCLK(clk)
);
end // block : rams
end // block: pointer_ram
endgenerate

Revision History
12/24/2010 - Initial Release

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
33566 Design Advisory Master Answer Record for Programmable Logic Based External Memory Interface Solutions for Virtex-6, Spartan-6, all 7 Series Devices, and all UltraScale based Devices N/A N/A
34266 Xilinx Virtex-6 MIG Solution Center - Design Assistant N/A N/A
42024 MIG 7 系列 DDR3 – FPGA 和 DDR3 SDRAM 之间的推荐迹线阻抗是什么？ N/A N/A
AR# 39549
日期 03/05/2013
状态 Active
Type 综合文章
器件 More Less
IP
People Also Viewed