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  3. AR# 39618: Design Assistant for XST - Inference concerns with Distributed RAM

AR# 39618

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Design Assistant for XST - Inference concerns with Distributed RAM

描述

Please refer to this Answer Record for help on understand how or why a dedicated RAM is inferred.

Note: This Answer Record is a part of the Xilinx Solution Center for XST (Xilinx Answer 38927). The Xilinx Solution Center for XST is available to address all questions related to XST. Whether you are starting a new design or troubleshooting a problem, use the Solution Center for XST to guide you to the right information.

解决方案

If you are intending to infer Distributed RAM and XST is failing to do so, then you may want to double check the following:
  • Compare your RTL to the "RAMs Coding Examples"of the XST user guide. The user guide will show you specific examples for Distributed RAM rather than Block RAM. See (Xilinx Answer 38931) for XST documentation.
  • If the Distributed RAM is pipelined, ensure that asynchronous resets are not used.
  • Double check in the Synthesis Report that the Distributed RAM is not being optimized out.
  • Make sure to not have a keep or save-net-flag constraint on the array that consists of the Distributed RAM. This will force XST to keep all of the registers instead of inferring a Distributed RAM.
  • Larger RAM depths may cause XST to infer Block RAM rather than Distributed RAM. You can force XST to infer a Distributed RAM by adding the RAM_STYLE constraint to the array. See (Xilinx Answer 39749) for help with attributes.
  • Be sure to not reset the entire array as this can not be done with Distributed RAM. You can only reset the output of the Distributed RAM or the pipeline stages since there are internal registers inside of the Distributed RAM are allowed to be reset.

If XST is inferring a Distributed RAM and you do not want this, then you can force XST to infer a Block RAM by using the RAM_STYLE constraint. If you want XST to infer registers rather than a RAM macro, then you can place a KEEP constraint on the entire array.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
38927 面向 XST 的 Xilinx 解决方案中心 N/A N/A

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
52250 14.2 TRCE/Timing Analyzer - Why is the clock of the write process used in the Timing report in the read path of Distributed RAM if this is asynchronous? N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
39134 Design Assistant for XST Inference concerns with RAM and ROM N/A N/A
AR# 39618
日期 12/15/2012
状态 Active
Type 综合文章
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