AR# 3992: FPGA Express - How do I implement a Synchronous Reset in VHDL or Verilog?
AR# 3992
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FPGA Express - How do I implement a Synchronous Reset in VHDL or Verilog?
描述
Keywords: FPGA Express, Foundation Express, set, reset, SR, SS, counter
Urgency: Standard
General Description: When Synchronous Reset or Set is implemented in a synchronous element like a register or a counter, synthesizing in FPGA Express will cause the following message to appear:
Inferred memory devices in process in routine jct_vhd line 18 in file 'H:/mydesign/counter.vhd'. =============================================================================== | Register Name | Type | Width | Bus | AR | AS | SR | SS | ST | =============================================================================== | COUNT_reg | Flip-flop | 8 | Y | N | N | N | N | N | ===============================================================================
With this code, the synchronous reset is implemented with an AND gate at the D input of registers (see FDR implementation in the Libraries Guide). This is functionally correct, but does not used the dedicated features of Xilinx devices.
To use the Synchronous Set/Reset pin of a flip-flop, use the Synopsys Attributes library. The sync_set_reset attribute is attached to single-bit signals with the attribute construct (VHDL) or compiler directive (Verilog).
This must be declared at the top of every VHDL entity that will use the sync_set_reset attribute:
library synopsys; use synopsys.attributes.all;
Then, attach the "sync_set_reset" attribute to the reset signal in every entity. Here is the section of VHDL code that will infer the synchronous reset:
architecture COUNT_ARCH of COUNTER is
signal COUNT: STD_LOGIC_VECTOR (7 downto 0); attribute sync_set_reset of RESET: signal is "true";
begin
process (CLK, RESET) begin if (CLK'event and CLK='1') then if (RESET='1') then COUNT <= "00000000"; else COUNT <= COUNT + 1; end if; end if; end process;
No library needs to be defined for Verilog. You will need to declare the attribute for every Verilog module. Here is the section of Verilog code that will infer the synchronous reset:
You will see the following change in the FPGA Express report:
Inferred memory devices in process in routine jct_vhd line 18 in file 'H:/mydesign/counter.vhd'. =============================================================================== | Register Name | Type | Width | Bus | AR | AS | SR | SS | ST | =============================================================================== | COUNT_reg | Flip-flop | 8 | Y | N | N | Y | N | N | ===============================================================================