2. 技术支持
  3. AR# 4046: Foundation Schematic Editor: Does Schematic Editor have multiple Undo capability?
  4. AR# 40464: Virtex-6 FPGA Integrated Block for PCI Express - PIO_RX_ENGINE.vhd does not accept 64-bit addressable memory writes

AR# 40464

|

Virtex-6 FPGA Integrated Block for PCI Express - PIO_RX_ENGINE.vhd does not accept 64-bit addressable memory writes

描述

Version Found: v2.2
Version Resolved and other Known Issues: See (Xilinx Answer 45723).

Due to a mistake in the PIO_RX_ENGINE.vhd file, the PIO example design does not accept 64-bit addressable memory writes. This is an issue only in the VHDL version.

解决方案

To fix this, look for theRX_MEM_WR64_FMT_TYPE state and remove the line assigning m_axis_rx-tready_int to 0. It is the line stating:

m_axis_rx_tready_int <= '0' after TCQ;

Change:

when RX_MEM_WR64_FMT_TYPE =>
m_axis_rx_tready_int <= '0' after TCQ;
if (m_axis_rx_tdata(9 downto 0) = "0000000001") then
state <= PIO_64_RX_MEM_WR64_DW1DW2 after TCQ;
else
state <= PIO_64_RX_RST_STATE after TCQ;
end if;


To:

when RX_MEM_WR64_FMT_TYPE =>
if (m_axis_rx_tdata(9 downto 0) = "0000000001") then
state <= PIO_64_RX_MEM_WR64_DW1DW2 after TCQ;
else
state <= PIO_64_RX_RST_STATE after TCQ;
end if;



Revision History
01/18/2012 - Updated; added reference to 45723
03/01/2011 - Initial Release


NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
45723 Virtex-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface Versions N/A N/A
AR# 40464
日期 05/20/2012
状态 Active
Type 已知问题
器件 More Less
IP
People Also Viewed