AR# 40650: 12.2 EDK, MPMC, Virtex-6, DDR3 - On-Die Termination Setting C_MEM_ODT_TYPE does not seem to work correctly.
AR# 40650
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12.2 EDK, MPMC, Virtex-6, DDR3 - On-Die Termination Setting C_MEM_ODT_TYPE does not seem to work correctly.
描述
MPMC always sets DDR3 mode register MR1[9, 6, 2] to "000" (RTT,nom disabled) after write leveling, even though I set MPMC parameter "C_MEM_ODT_TYPE" to enable ODT. How do I enable ODT with MPMC?
解决方案
There is an error in MPMC HDL code of the versions below. v5.03.a v5.04.a v6.00.a v6.01.a v6.02.a v6.03.a
Because of this error, MPMC always sets MR1[9, 6, 2] to "000" (RTT,nom is disabled). Instead, MR2[10:9] is set to "10" (RZQ/2). While RTT,nom is disabled, RTTwr is enabled, providing the expected ODT termination during write commands.
To work around this issue, you can modify the HDL code manually.
1. Copy the MPMC core to the local pcores/ directory from <EDK Install Path>\hw\XilinxProcessorIPLib\pcores\mpmc_vX_XX_a
2. Open the pcores\mpmc_vX_XX_a\hdl\verilog\mpmc_core.v file
3. Search these line and modify.
From: localparam P_DDR2_RTT_WR = "0"; // ODT Write termination value To: localparam P_DDR2_RTT_WR = "OFF"; // ODT Write termination value
From: localparam P_DDR3_RTT_WR = "0"; // ODT Write termination value To: localparam P_DDR3_RTT_WR = "OFF"; // ODT Write termination value
From: .RTT_WR (P_DDR2_RTT_WR), To: .RTT_WR (P_DDR3_RTT_WR),