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  3. AR# 4136: 12.1 Constraints - How do I initialize the contents of a RAM primitive via a constraint file?
  4. AR# 41363: 13.1 EDK - Incorrect Bus2IP_Resetn polarity in user_logic.v generated by CIP Wizard

AR# 41363

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13.1 EDK - Incorrect Bus2IP_Resetn polarity in user_logic.v generated by CIP Wizard

描述

When I use the Verilog version user_logic generated by CIP Wizard in 13.1 version, I cannot access the custom IP.

解决方案

The 13.1 software version CIP Wizard generated user_logic.v has an incorrect polarity setting on "Bus2IP_Resetn" as below:

// implement slave model register(s)
always @( posedge Bus2IP_Clk )
begin: SLAVE_REG_WRITE_PROC

if ( Bus2IP_Resetn == 1 )
begin
slv_reg0 <= 0;
end

The "Bus2IP_Resetn" is active "low" according to data sheet and its name. Changing the condition of "Bus2IP_Resetn == 1" to "Bus2IP_Resetn == 0" will resolve the problem. The VHDL version user logic is correct.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
39843 13.x EDK - Master Answer Record N/A N/A
AR# 41363
日期 12/15/2012
状态 Active
Type 综合文章
Tools
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