When I generate a bitstream for a 7 Series device, the following error message occurs:
ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD).This maycause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected.To prevent this error, it is highly suggested to specify all pin locations and I/O standards to avoid potential contention or conflicts and allow proper bitstream creation.To demote this error to a warning and allow bitstream creation with unspecified I/O location or standards, you can apply the following bitgen switch: -g UnconstrainedPins:Allow"
For example, this message applies to the following I/O ports:
The 13.2 BitGen software introduces this change to protect devices from accidental damage that could be caused by the tools randomly choosing a pin location or IOSTANDARD without knowledge of the board voltage or connections.
For example:
The default I/O standard for the 7 Series is LVCMOS18 for single-ended signals for all banks, the default I/O standard was LVCMOS25 in previous architectures.
As the message indicates, the error can be downgraded to a warning by setting the -g UnconstrainedPins:Allow switch in either of the following:
However, you must ensure that all the pins are in the appropriate locations. The Pinout Report (.pad) lists the location of the pins after PAR as well as the IOSTANDARD.
If the IOSTANDARD is listed with an asterisk (*), for example, LVCMOS18*, then the IOSTANDARD was undefined by the user and the software used a "default" setting.
You need to ensure that this IOSTANDARD is compatible with the voltages, terminations, and connectivity of the board before down grading the warning.
Note: A "default" IOSTANDARD is applied during Map/Par to provide an output .ncd for the analysis tools (Timing, Power, etc.), however IOSTANDARDs must be specified or BitGen will error out with the above error.
Note: The recommended user flow is to select all IOSTANDARDs and pin placements in the design, for example, the UCF file.
Do not place LVCMOS18 in High Range banks that are powered at 2.5V or 3.3V.
Xilinx IP Cores
Some Xilinx IP cores might be affected by this problem when implementing the example design included with the core.| (Xilinx Answer 42830) | 7 Series Integrated Block Wrapper v1.1 Rev 1 for PCI Express - sys_reset_n not does not have a pin location constraint |
| (Xilinx Answer 42665) | MIG 7 Series v1.2 - Why does the MIG Example Design fail in BitGen? |
| (Xilinx Answer 42844) | SPI-4.2 v11.2 (AXI) - Why does the SPI-4.2 Example Design fail in BitGen when targeting Virtex-7 or Kintex-7 devices? |
| (Xilinx Answer 42847) | Tri-Mode Ethernet MAC v5.1 - Why does the Example Design fail in BitGen when targeting Virtex-7 or Kintex-7 devices? |
| (Xilinx Answer 42848) | 10-Gigabit Ethernet MAC v11.1 - Why does the Example Design fail in BitGen when targeting Virtex-7 or Kintex-7 devices? |
| (Xilinx Answer 42849) | Ten Gigabit Ethernet PCS/PMA (10GBASE-R) v2.1 - Why does the Example Design fail in BitGen when targeting Virtex-7 or Kintex-7 devices? |
| (Xilinx Answer 42850) | RXAUI v2.1 and XAUI v10.1 - Why does the Example Design fail in BitGen when targeting Virtex-7 or Kintex-7 devices? |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 42844 | SPI-4.2 v11.2 (AXI) - Why does the SPI-4.2 Example Design fail in bitgen when targeting Virtex-7 or Kintex-7 devices | N/A | N/A |