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  3. AR# 42850: RXAUI v2.1 and XAUI v10.1 - Why does the Example Design fail in bitgen when targeting Virtex-7 or Kintex-7 devices

AR# 42850

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RXAUI v2.1 and XAUI v10.1 - Why does the Example Design fail in bitgen when targeting Virtex-7 or Kintex-7 devices

描述

When I generate a Virtex-7 or Kintex-7 device bitstream for the XAUI or RXAUI example design, the following error message occurs:

"ERROR:Bitgen:342-This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To prevent this error, it is highly suggested to specify all pin locations and I/O standards to avoid potential contention or conflicts and allow proper bitstream creation. To demote this error to a warning and allow bitstream creation with unspecified I/O location or standards, you can apply the following bitgen switch: -gUnconstrainedPins:Allow."

解决方案

Starting in ISE 13.2 software this error message occurs if any of the pins do not have a location constraint or IOSTANDARD assigned.

For more information about the error message and how to downgrade this to a warning message if needed, please refer to (Xilinx Answer 41615).

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
40630 LogiCORE IP RXAUI v2.1 - Release Notes and Known Issues for the 13.1 ISE Software N/A N/A
40631 LogiCORE IP XAUI v10.1 - Release Notes and Known Issues for ISE Design Suite 13.1/13.2/13.3 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
41615 7 Series, BitGen (13.2 and later) - "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)" N/A N/A
AR# 42850
日期 12/15/2012
状态 Active
Type 综合文章
IP
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