The following answer records cover current known issues as well as commonly asked questions related to Aurora 64B/66B.
Note: This Answer Record is part of the Xilinx Aurora Solution Center (Xilinx Answer 21263).
The Xilinx Aurora Solution Center is available to address all questions related to Aurora.
| (Xilinx Answer 54368) | LogiCORE IP Aurora 64B66B - Release Notes and Known Issues for Vivado 2013.1 and later tool versions |
Known Issues
| (Xilinx Answer 50101) | LogiCORE IP Aurora 64B66B v6.2 - Targeting Aurora 64B66B core for Hot plug applications using Virtex-6 GTH transceivers |
| (Xilinx Answer 43713) | Virtex-6 GTH Aurora 64b/66b - RXBUFRESET and BUFFER_CONFIG_LANEx Updates |
| (Xilinx Answer 50885) | LogiCORE IP Aurora 64B66B v7.2 - Compile error while using the script implement_synplify.bat/implement_synplify.sh to implement the example design |
| (Xilinx Answer 47304) | Aurora 8B10B v8.1/64B66B v7.1 and 7-series Transceiver Wizard (ISE 14.1/Vivado 2012.1) - How to generate Aurora cores/GT wrappers for XQ7VX690T/TL RF1930 device? |
| (Xilinx Answer 43723) | 7 Series Aurora 64B66B V6.1 - Core Generation Errors for Virtex-7 XT Devices |
| (Xilinx Answer 34190) | Virtex-6 GTX Aurora 64b/66b - MAP errors out due to incorrect MMCM attributes |
| (Xilinx Answer 57021) | 7 Series, Aurora 64B/66B V 7.3/8.0 - Hot-plug circuit fails to trigger reset when valid characters are not received by the core |
| (Xilinx Answer 43591) | Design Advisory for Virtex-6 FPGA GTH Transceivers - Updates Required to Address RXBUFRESET-Related Initialization Sequence and BUFFER_CONFIG_LANEx Issues |
| (Xilinx Answer 52381) | LogiCORE IP Aurora 64B66B v7.1 - DRC error is observed while running timing simulation for few configurations |
| (Xilinx Answer 45637) | Virtex-6QL Aurora 64B/66B v6.2 - "ERROR:sim - Failed to initialize IP model |
| (Xilinx Answer 42803) | Aurora 64b/66b - BitGen errors in 13.2 |
| (Xilinx Answer 42190) | Aurora 64b/66b - Soft errors after reset de-assertion |
| (Xilinx Answer 42034) | Aurora 64b/66b - Reduction of BUFGs in Virtex-5 and Virtex-6 GTX devices |
| (Xilinx Answer 39962) | Virtex-6 GTX Aurora 64B/66B v5.1 - Incorrect setting for PMA_CDR_SCAN |
| (Xilinx Answer 39645) | Virtex-6 GTX Aurora 8B/10B/Aurora 64b/66b - Auto Link recovery during hot-plug |
| (Xilinx Answer 38492) | Aurora 8b/10b 64b/66b - "ERROR:PhysDesignRules:2270 when forwarding REFCLK over unused tiles" |
| (Xilinx Answer 37999) | Aurora 64b/66b v4.1 - Simulation and Hardware always held in reset |
| (Xilinx Answer 37592) | Virtex-6 Aurora 64b/66b - Data loss in the RX side |
| (Xilinx Answer 37591) | Aurora 64b/66b - No USER_CLK for TX-only Simplex core |
| (Xilinx Answer 37038) | Aurora 64b/66b - TX_DST_RDY_N deasserts 2 cycles after every 32 cycles |
| (Xilinx Answer 36328) | Aurora 8b/10b 64b/66b - REFCLK error occurs when creating core in different OS than the XCO file |
Release Notes
| (Xilinx Answer 35371) | Aurora 64B/66B v4.1 - Release Notes and Known Issues for ISE Design Suite 12.1 |
| (Xilinx Answer 39764) | Aurora 64B/66B v5.1 - Release Notes and Known Issues for ISE Design Suite 12.4 (AXI4-stream) |
| (Xilinx Answer 42624) | Aurora 64B/66B v4.2 - Release Notes and Known Issues for ISE Design Suite 13.1 |
| (Xilinx Answer 42804) | Aurora 64B/66B v6.1 - Release Notes and Known Issues for ISE Design Suite 13.2 (AXI4-stream) |
| (Xilinx Answer 45671) | Aurora 64B/66B v6.2 - Release Notes and Known Issues for ISE Design Suite 13.4 (AXI4-stream) |
| (Xilinx Answer 47704) | LogiCORE IP Aurora 64B/66B v7.1 - ISE 14.1/VIVADO 2012.1 - Release Notes and Known Issues |
| (Xilinx Answer 52313) | LogiCORE IP Aurora 64B/66B v7.3 (ISE 14.3/VIVADO 2012.3), v7.3 Rev1 (VIVADO 2012.4) - Release Notes and Known Issues |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 45714 | Aurora 64B66B V6.2 ? Timing simulation failures & TRACE errors | N/A | N/A |
| AR# 42552 | |
|---|---|
| 日期 | 04/06/2017 |
| 状态 | Active |
| Type | 综合文章 |
| IP | |