2. 技术支持
  3. AR# 4256: M1.x EPIC - Adding readback capability
  4. AR# 42569: Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.3

AR# 42569

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Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.3

描述

This article contains issues resolved in theSpartan-6 FPGA Integrated Block v2.3 Wrapper for PCI Express that are alsolisted in the readme.txt file that accompanies this version of the core. These are issues that were fixed as part of the update from the previous version of the core.

For other known and resolved issues that may not be in this list see(Xilinx Answer 45702).

解决方案

Resolved Issues

  • GTP Settings Updated
    CR 608469
    The GTP settings have been updated, based on board characterization results, with the new settings providing better reliability and more margin across PVT.
  • LL_REPLAY_TIMEOUT Settings Updated
    CR 582996
    The LL_REPLAY_TIMEOUT settings have been updated to account for RX L0s Latency.
  • User Interface Signal name changed from tstrb to tkeep.
    CR 579318
    User Interface Signals s_axis_tx_tstrb[3:0] and m_axis_rx_tstrb[3:0] have been renamed to s_axis_tx_tkeep[3:0] and m_axis_rx_tkeep[3:0]. These signals are not needed for the Spartan-6 FPGA Integrated Block for PCI Express. However, these are needed for AXI compliance.
  • Root Port Model - GTX Settings Updated
    CR 590671
    The POWER_SAVE setting on the GTX in the Virtex-6 FPGA Integrated Block for PCI Express Root Port model has been updated.

Revision History
01/18/2012 - Modified format to use a single AR for all known issues and referenced 45702 for all known issues. Any issue that was listed here is now in AR 45702.
10/08/2011 - Added 44442
07/06/2011 - Initial Release

链接问答记录

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
42454 Spartan-6 FPGA Integrated Block for PCI Express - CORE Generator GUI shows a value of 0 for bit 15 of the Device Capabilities Register N/A N/A
42339 Spartan-6 FPGA Integrated Block for PCI Express - What is the PMA_RX_CFG setting for an asychronous link? N/A N/A
42749 Spartan-6 FPGA Integrated Block for PCI Express - Some Bits of m_axis_rx_tuser Not Defined in User Guide N/A N/A
AR# 42569
日期 05/20/2012
状态 Active
Type 版本说明
器件
IP
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