AR# 42714

描述

The design uses an 'include file that is required by several sources, but not explicitly included by all of them (i.e. a global include file).

The order of compile is critical, and this include file must be compiled before the other files that require it (due to parameters being used in those source files that are defined in the include file).

When I add all the source files to the project including the "global" include file, and then use the "Specify Top Module" function, there is not a single top listed.

In addition, there are a series of parser errors output to the terminal due to undefined parameters in the source files.

解决方案

PlanAhead tool 13.1 does not have a global include option and the 'include needs to be explicitly entered in each file that requires the use of the include file.

In PlanAhead tool 13.2 a Verilog file can be specified as the Global Include in the "Source File Properties" of the Verilog Source or by using the Tcl command below:

set_property is_global_include true <my_file>.v