AR# 42906

Changes in v6.04.a, introduced in 13.2.

Note: Unless specified, limitations and resolved issues affect all previous versions.

13.2 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)

13.2 - Changes in tool interface files (.mpd)

13.2 - Changes in Tcl script files associated with core (.tcl)

13.2 - Changes in IP Configuration GUI (.ui)

• [<CR592851>] Updated Virtex-6 enumerations for Output Drive Strength. The values of RZQ/6 and RZQ/7 were swapped in the GUI. RZQ/7 -- C_MEM_REDUCED_DRV(0), and RZQ/6 -- C_MEM_REDUCED_DRV(1).

13.2 - Changes in documentation associated with core

• Updated documentation links, revision history, and fixed typographical errors.

• [<CR579241>] Added VFBC clarification on simultaneous read/write abilities.

• [<CR595958>] Added simulation considerations: An explicit note that structural simulations is not supported (limitation of MIG.) Weak pull-downs might be necessary in certain top level language/simulators combinations in order for calibration to successfully complete (stops X propagations.)

• [<CR606195>] Updated path locations of MIG files to accurately reflect their actual locations.

• [<CR607433>] Clarified Spartan-6 LPDDR RZQ/ZIO recommended parameter/signal combinations. C_MEM_CALIBRATION_SOFT_IP = TRUE, C_MEM_SKIP_IN_TERM_CAL = 1, C_MEM_SKIP_DYNAMIC_CAL = 0, RZQ should be connected, ZIO should be omitted.

• [<CR608972>] Added special restrictions on source of MPMC_PLL_Lock input. The MPMC_PLL_Lock must be driven directly from the PLL providing the memory clocks for the IP. If their is any logic between the output of the PLL and the input on MPMC, then a Place and Route DRC will produce an implementation error.