AR# 42987

描述

The quality of the reference clock supplied to the PLL in the Virtex-6 GTH FPGA Transceiver can greatly impact the performance of the transmit jitter and receive jitter tolerance. Jitter or phase noise from the reference clockplays an important roll indetermining this performance; phase noise being the preferred specification method as it allows the designer to incorporate thevarious frequency components that a time-based jitter specification might overlook.

This answer record contains the reference clock phase noise limits that Xilinx recommends based on the PLL settings being used.

解决方案

Depending on the reference clock being used, a different mask needs to be applied. The table below describes the points of a mask above which the reference clock phase noise should not exceed. If a reference clock does exceed these masks, it results in additional jitter on TX data.

NOTE: If your desired reference clock rate is not listed in the table above, please use the phase noise mask for the nearest reference clock frequency.

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