AR# 43131

描述

After setting the "Design Entry" setting for CORE Generator project to "Schematic" and generating an IP core. It does not appear that the schematic symbol is generated correctly.

After adding the generated core by way of XCO to an ISE project, the Symbol can be very large in some cases and the data buses are not labeled at all as they should be.

解决方案

In cases where theschematic symbol is not created, or created as desired during core generation,a new symbol can be generated as follows.

• Add the VHDL/Verilog wrapper file into the ISE project and create a schematic for that file from within ISE. This creates a sensible size schematic with data buses labeled as expected.