AR# 43356

描述

This part of the MIG Design Assistant will guide you to information on performing reads to the User Interface.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243).The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

Driving Read on the User Interface

The read path of the User Interface uses a simple 64-deep FIFO structure to hold data returning from a Read transaction. The empty flag (pX_rd_empty) from the Read Data FIFO can be used as a data valid indicator. Whenever pX_rd_empty is deasserted, there is valid data present on the pX_rd_data bus. To transfer data into the FPGA logic from the Read Data FIFO, the pX_rd_en signal must be asserted on the rising edge of pX_rd_clk. The pX_rd_data bus transitions on the rising edge of pX_rd_clk. The pX_rd_en signal can remain asserted at all times and the pX_rd_empty signal can be used as a data valid indicator, if desired.

The pX_rd_overflow signal indicates to the user that the memory has returned more data than fits into the read data FIFO and that data was lost. To implement a Read transaction, the Read Data FIFO must have enough space to complete the request as dictated by the burst length value that is entered into the Command FIFO. Otherwise, an overflow condition occurs when the transaction tries to execute.

Additional Information

For timing diagrams and more information, see UG388 under "MCB Operation > Memory Transactions > Simple Read".

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