AR# 43520

描述

Determining a root cause for a hardware issuecan be a time consuming process.With memory interface designs, general board layout, adherence to MIG layout, pin-out, and banking rules, extreme care in SI simulation using IBIS models are key steps in ensuring proper behavior in hardware.For information on these check points,see the MIG Design Assistant - Spartan-6 Hardware at(Xilinx Answer 37502).

Once these items have been verified, this answer record should serve as a starting point for debugging calibration failures, data errors, and general board level issues.

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you're starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

Before investigating calibration failures or data errors, users should go through the General Board Level Debug section of this Design Assistant to ensure a functional board and layout.

General Board Level Debug

• (Xilinx Answer 43521)

Once the board layout is verified, the next step in hardware debug is to load the provided MIG Example Design with the Debug Port enabled on the board. The Debug Port includes critical debug signals brought up through ChipScope modules that are used in this debug flow. To enable the Debug Port, generate your MIG design and Enable the Debug Signals for Memory Controller on the FPGA Options GUI screen. For more information on the debug port, see (Xilinx Answer 43539).

The Example Design is a known working design with a fully operational Traffic Generator. The Traffic Generator sends out write commands, reads back the data, and performs a comparison to ensure a working system. The Traffic Generator can be configured to send many different types of data patterns to test for different board related issues such as SSO and Cross-Talk. For information on the Traffic Generator and it's patterns, please see theMIG Example Design with Traffic Generator (CORE Generator Tool Native Interface Only) section of the Spartan-6 FPGA Memory Interface
Solutions User Guide(UG416):http://www.xilinx.com/support/documentation/ip_documentation/mig/v3_8/ug416.pdf

Once the Example Design is running in your hardware, there are a few simple checks to determine the high-level failure.Monitor thecalib_done signaland error flags to determine if a calibration or bit/data error has occurred.

Initial Checks

Are the clocks toggling?

• Check that thePLL_ADV is locked (pll_lock in infrastructure.v).
• Verify input PCB clock sources and output CK/CK# using an oscilloscope.
• Check the reset polarity of the design.
• Check that the RST_ACT_LOW parameter value is correct.
• Check that the nCS signal to the memory devices is pulled down or driven Low by the FPGA.

Debugging Calibration Failures - (Xilinx Answer 43537)

Debugging Data Errors - (Xilinx Answer 43538)

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