AR# 43531: Virtex-6 FPGA Integrated Block for PCI Express - When I simulate a VHDL x8 Root Port, the example design does not link up until around 122 microseconds
AR# 43531
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Virtex-6 FPGA Integrated Block for PCI Express - When I simulate a VHDL x8 Root Port, the example design does not link up until around 122 microseconds
描述
Version Found: v2.3 Version Resolved and other Known Issues: See (Xilinx Answer 45723).
When I simulate a VHDL x8 Root Port, the example design does not link up until around 122 microseconds.
解决方案
Make the following changes in the 'board.vhd' file (in the generated core's functional directory).
From:
LINK_CAP_MAX_LINK_WIDTH => X"01", LTSSM_MAX_LINK_WIDTH => X"01", To:
LINK_CAP_MAX_LINK_WIDTH => X"08", LTSSM_MAX_LINK_WIDTH => X"08", This change speeds up the simulation link up time. This issue is fixed in the v2.5 core release.
Revision History 01/18/2012 - Updated; added reference to 45723 12/14/2011 - Initial Release
Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.