AR# 43593

描述

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

Interface Width

The AXI Read and Write data width can be 32, 64, or 128. It must be equal to the MCB data width. The MCB data width can be 32, 64, or 128 bits, depending on the MCB configuration.

Interface Clock

Each AXI4 slave interface can run with a completely independent clock from each other and from the memory clock. All AXI channels and interface logic within a specific AXI4 slave interface use the same clock, with no additional clock conversion before passing into the associated MCB port.

Address Width

The address width must be parameterized to support the desired system address bus width. If the system address bus is defined wider than the memory size, it is acceptable to alias/wrap the memory across the address space. The MCB interface supports a maximum of 30 bits for the address bus. The MSB of the AXI address is cut off, if necessary. A 32-bit constant address width is used for compatibility with EDK. The address also wraps if the address range specified by the base and high address is smaller than the memory size.

Read-Only or Write-Only AXI Ports

Each AXI4 interface can be configured as Read-only or Write-only even when connected to a bidirectional MCB port. This permits logic optimization when bidirectional data flow is not required. The Read-only or Write-only AXI port is required when connected to a unidirectional MCB port. When placed in Read-only or Write-only mode, unnecessary Read/Write arbitration logic and datapath logic are removed. If the MCB port is natively a bidirectional port, the MIG GUI and source RTL allow you to choose a Read-only or Write-only AXI4 interface for FPGA resource savings.

Reset

The AXI4 interface has a single synchronous reset, active low signaling, that resets the entire core and brings it to a known initialized state. A reset event causes a full reset including recalibration of the controller.

Bursts

The following burst rules apply:

• The AXI Spartan-6 FPGA DDRx Memory Controller supports INCR and WRAP bursts including AXI4 extensions of INCR burst up to 256 data beats.
• Attempting FIXED bursts does not hang the AXI4 interface, but a FIXED burst does not have a logical meaning for a memory controller. For simplicity, FIXED burst commands result in an INCR command. No errors are flagged.
• Supports burst size down to 1 byte wide burst. Burst sizes below the native data width of the MCB port controller datapath is called a subsize burst or narrow transfer. Subsize burst is supported, but the AXI protocol defines a subsize burst to have data rotate through the correct byte lanes. Narrow burst support is conditional. If the system has no masters that produce narrow bursts, then significant logic can be reduced by removing support for the narrow bursts. This is controlled by the C_S<Port_Num>_AXI_SUPPORTS_NARROW_BURST parameter.
• The AXI Spartan-6 FPGA DDRx Memory Controller can assume that bursts do not cross a 4 KB address boundary as defined in the AXI4 specification. However, a burst that crosses a 4 KB boundary does not hang the interface, but it can cause that transaction to have undefined behavior on memory contents.

Cache Bits

The following cache bit rules apply:

• The AXI Spartan-6 FPGA DDRx Memory Controller does not implement bridging, speculative pre-fetching, or L2 caching functions so it can ignore all CACHE bits and treat them as 00000.
• The AXI Spartan-6 FPGA DDRx Memory Controller attempts to return B Responses as soon as possible without violating AXI ordering rules to reduce latency to master waiting for B Responses.
• Because the AXI Spartan-6 FPGA DDRx Memory Controller is connected to a multi-ported hard memory controller, it must not issue a B Response until the Write has completed to memory. The B response must guarantee that another Write or Read. Another MCB port that accesses the same memory location could not complete ahead of the current Write transaction. The parameter C_S<Port_Num>_AXI_STRICT_COHERENCY can be set to 0 to relax write coherency checking so that the B Response is returned earlier when the transaction is known to have completed relative to that port instead of being delayed to ensure the write completes across all ports.For more information, please see the EDK Flow Details section in Spartan-6 FPGA Memory Interface Solutions User Guide.

Protection Bits

The AXI Spartan-6 FPGA DDRx Memory Controller ignores the AXI PROT bits and assume all transactions are normal, non-secure accesses.

Exclusive Access

This IP does not currently support exclusive access.

Response Signaling

The AXI Spartan-6 FPGA DDRx Memory Controller always generates an OKAY response.

IDs, Threads, and Reordering

The MCB interface is strictly linear; therefore, no reordering or threads is implemented in the bridge. Transactions are returned in the exact order they are received.

Read/Write Acceptance Depth

The read acceptance depth is five outstanding transactions. The write acceptance depth is four outstanding transactions.

Read/Write Arbitration

AXI has separate read and write channels. An external memory has only a single address bus. Therefore, the AXI Spartan-6 FPGA DDRx Memory Controller must arbitrate between coincident Read and Write requests to determine which one to execute to memory. The arbitration algorithm for Read and Write requests is Round-Robin.

Endianess

The AXI Spartan-6 FPGA DDRx Memory Controller is little-endian only.

Region Bits

The AXI Spartan-6 FPGA DDRx Memory Controller does not have to make use of REGION bits and can ignore this signal.

Low Power Interface

The AXI Spartan-6 FPGA DDRx Memory Controller does not support alow power interface.

Limitations

The AXI Spartan-6 FPGA DDRx Memory Controller does not support QoS.

For more information regarding the AXI interface, please see the Spartan-6 FPGA Memory Interface Solutions User Guide (UG416), in particular, the EDK Flow Details > AXI Spartan-6 FPGA DDRx Memory Controller section.

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