2. 技术支持
  3. AR# 4365: 4.2i Foundation HDL Editor - I am unable to synthesize a top-level VHDL or Verilog file from HDL Editor
  4. AR# 43656: Virtex-6 FPGA Broadcast Connectivity Kit - Known Issues and Release Notes Master Answer Record

AR# 43656

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Virtex-6 FPGA Broadcast Connectivity Kit - Known Issues and Release Notes Master Answer Record

描述

This Answer Record lists all known issues with the Virtex-6 FPGA Broadcast Connectivity Kit. 

解决方案

To see the Design Advisories associated with the Virtex-6 FPGA Broadcast Connectivity Kit, please see (Xilinx Answer 38760) Design Advisory Master Answer Record for Virtex-6 FPGA Broadcast Connectivity Kit.

The Virtex-6 FPGA Broadcast Connectivity Kit Design Advisory Master Answer Record forms part of (Xilinx Answer 43745) Xilinx Boards and Kits Solution Center - available to address all questions related to Xilinx Boards and Kits.

(Xilinx Answer 43655)Virtex-6 FPGA Broadcast Connectivity Kit - FMC card reference clock from Si5324 device
(Xilinx Answer 50596)Xilinx Evaluation Kits - PCIe cards - CE requirements for PC test environment

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
43750 Xilinx 电路板和套件解决方案中心 — 热门问题 N/A N/A

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
43655 Virtex-6 FPGA Broadcast Connectivity Kit - FMC card reference clock from Si5324 device N/A N/A
38683 Virtex-6 广播连接功能套件的设计咨询 - ML605 板物料清单更改会导致 SDI 演示问题 N/A N/A
50596 Xilinx Evaluation Kits - PCIe Cards - CE Requirements for PC Test Environment N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
43655 Virtex-6 FPGA Broadcast Connectivity Kit - FMC card reference clock from Si5324 device N/A N/A
38683 Virtex-6 广播连接功能套件的设计咨询 - ML605 板物料清单更改会导致 SDI 演示问题 N/A N/A
38760 Design Advisory Master Answer Record for Virtex-6 FPGA Broadcast Connectivity Kit N/A N/A
AR# 43656
日期 09/18/2017
状态 Active
Type 已知问题
Boards & Kits
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