AR# 44113

描述

解决方案

Starting from the design that 13.2 BSB creates, follow the manual steps below to get to a working design:

1. Flash size is 128M (not 32M), modify it in the XPS/Addresses tab.
2. Add external port 'linear_flash_adv_b'
3. In the system.ucf, add: NET Linear_Flash_adv_n LOC = "M30" | IOSTANDARD = "LVCMOS25";
4. In system.mhs add: PORT Linear_Flash_adv_n = net_gnd, DIR = O
5. Bit-flip the flash data bus in the system.ucf: D0->D15,... D15->D0
6. Bit-flip the flash address bus in system.ucf: A0->A25,... A25->A0
7. Remove the Linear_Flash_invertor from the mhs and connect the axi_emc port CE_N directly to the port.
8. Make sure that the DIP Switch on the KC705 board for M0 is set to LOW, otherwise, the Linear Flash will be disabled.

The plan is to fix this issue on BSB designs starting with the EDK 13.3 software.

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