AR# 44488

描述

解决方案

Introduction

For installation instructions for this release, please go to:
www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

For system requirements:
www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm

This file contains release notes for the Xilinx LogiCORE IP Virtex-6 FPGA GTH Transceiver Wizard v1.9 solution. For the latest core updates, see the product page at:
www.xilinx.com/content/xilinx/en/products/intellectual-property/v6_fpga_gth_transceiver_wizard.html

New Features

• ISE 13.3 software support
• Post-PAR netlist simulation support
• Auto-upgrade feature to upgrade from v1.2, v1.3, v1.4, v1.5, v1.6, v1.7, v1.8 to v1.9
• Added support for higher refclk Fmax (up to 700 MHz) for -2,-3 speed grade device and (up to 645 MHz) for -1 speed grade. For more information please see (Xilinx Answer 41022).

Supported Devices

The following device families are supported by the core for this release.

• Virtex-6 xc6vhx255t
• xc6vhx380t
• xc6vhx565t

Resolved Issues

Fixed CRs:

• # 614187 - RX_BUF_RESET pulse in GTH Reset sequence is too short.
• # 615765 - BUFFER_CONFIG_LANEx must be set to manual adjustment mode based on TX/RX_FABRIC_WIDTH to avoid errors after power-up or configuration
• # 622772 - Default value of PMA_LPBK_CTRL_LANEx needs to be updated to 'h0002
• # 621026 - Attribute DFE_TRAIN_CTRL_LANEx needs to brought out to mgt wrapper
• # 622397 - Connect RXBUFRESET of lanes 1/2/3 to rxbufreset when GTHX4LANE = 1

Known Issues:

The following are known issues for v1.9 of this core at time of release:

• To implement a design targeting a reference clock higher than 670 MHz (for -2, -3 speed grades) or 623MHz (for -1 speed grade), please see (Xilinx Answer 41022).
• The user guide ug691_v6_gthwizard.pdf is not updated for this version of core.
• Limited hardware testing was done for the Virtex-6 GTH Wizard on ML627 board.
• Attribute and port settings for OTU-4 are applicable to single lane only. You must integrate other OTU-4 compatible logic manually in your design.
• For 16 and 20 bit datapath widths, multiple line rates and multiple datapath widths cannot be selected accross multiple lanes.

The most recent information, including known issues, workarounds, and resolutions for this version is provided in the IP Release Notes Guide.

Technical Support

To obtain technical support, create a WebCase at www.xilinx.com/support. Questions are routed to a team with expertise using this product.

Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.

Additional Information

This version of the wizard supports Production silicon only. Using a wrapper generated with this version of the wizard to program a CES Virtex-6 HXT device is not supported. Please use v1.7 of this wizard to program CES devices. Refer to (Xilinx Answer 41464) for guidance on how to distinguish Production from ES devices and for additional details.

Core Release History

Date By Version Description
================================================================================
10/26/2011 Xilinx, Inc. 1.9 ISE 13.3 support
10/26/2011 Xilinx, Inc. 1.7(Rev2) ISE 13.3 support
06/22/2011 Xilinx, Inc. 1.8(Rev1) ISE 13.2 support
04/08/2011 Xilinx, Inc. 1.8(Rev0) ISE 13.1 support
04/08/2011 Xilinx, Inc. 1.7(Rev1) ISE 13.1 support
03/01/2011 Xilinx, Inc. 1.7 ISE 13.1 support
12/14/2010 Xilinx, Inc. 1.6 ISE 12.4 support
09/21/2010 Xilinx, Inc. 1.5 ISE 12.3 support
07/23/2010 Xilinx, Inc. 1.4 ISE 12.2 support
04/19/2010 Xilinx, Inc. 1.3 ISE 12.1 support
12/02/2009 Xilinx, Inc. 1.2 ISE 11.4 support
09/16/2009 Xilinx, Inc. 1.1 Initial release
================================================================================

链接问答记录

相关答复记录