描述
I am trying to simulatethe AXI HWICAP, however, it looks that the data read arrives ahead in one clock cycle. Is this a known issue? When can I expect a fix for it?
解决方案
This is a known issue with UNISIM simulationmodel. The data read from the UNISIMmodel arrives one clock cycle tooearly. This affects Virtex-6 ICAP simulations only and does not impact the hardware functionality. This issue is planned to be fixed starting in the EDK 13.3 software release.