AR# 44596

描述

This Answer Record contains the Release Notes for the Aurora 8B/10B v7.12 Core, released in ISE 13.3, and includes the following:

• New Features
• Bug Fixes
• Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide.

解决方案

New Features

• Virtex-7/Kintex-7 family support
• ISE 13.3 software support
• Cadence Incisive Enterprise Simulator (IES) support
• Synopsys Synplify Pro support

Supported Devices

• Virtex-7
• Virtex-7 -2L
• Virtex-7 -2G
• Kintex-7
• Kintex-7 -2L
• Virtex-6 XC CXT/LXT/SXT/HXT
• Virtex-6 XQ LXT/SXT
• Virtex-6 -1L XC LXT/SXT
• Spartan-6 XC LXT
• Spartan-6 XA
• Spartan-6 XQ LXT

Resolved Issues

• Line rate at 1,5625G with Refclk at 156.25 Mhz does not generate a Spartan-6 core
  • CR number 593355
• Symgen and Symdec modules need to be fixed for validation failures
  • CR number 589397
• Negate RESET signal in example design top
  • CR number 608652
• Update Virtex-6 PMA_RX_CFG settings as Async protocol
  • CR number 590720
• Remove simplex-both option from core altogether
  • CR number 608664
• CLK25_DIVIDER_0/1 attribute values are always set to 1 for Spartan-6
  • CR number 615434
• VHDL version does not have the correct implementation of sof generation
  • CR number 616007
• Lint Errors
  • CR number 616010
• Aurora 8b/10b UG766 v6.2 - Latency numbers should be in USRCLK cycles
  • CR number 595325
• Aurora 8b/10b - Spartan-6 should have possibility to use REFCLK other tile
  • CR number 586686
• Aurora 8B/10B - Please add RXEQMIX setting to GUI and bring it to the top level in the Aurora files
  • CR number 596391
• Aurora 8B/10B - Please add option to make DRP available at Aurora top level
  • CR number 596391