Outstanding Known Issues inSynplify 13.3
(Xilinx Answer 44208) - Performance degradation of Xilinx Transceivers when using SystemVerilog with Synplify tool
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
39243 | ISE Design Suite 13 - Known Issues | N/A | N/A |
AR# 44684 | |
---|---|
日期 | 05/22/2012 |
状态 | Active |
Type | 已知问题 |
Tools |