AR# 45071

描述

解决方案

The fan control circuitry on the revision C KC705 Evaluation Board uses two FPGA pins to control the performance of the FPGA cooling fan. These pins are pin U22 and pin L26.

Pin U22 monitors the SM_FAN_TACH signal. This signal is an input into the FPGA that delivers information about the fan's current rotational speed.

Pin L26 drives the SM_FAN_PWM signal. This signal is an output from the FPGA and drives a PWM pulse into the fan control circuit to enable the fan to spin properly. If pin L26 is completely unused in a customer design, the default ISE behavior is for thepin to be pulled low. When configured as pull-down, pin L26 interferes with the fan control circuit, and the fan will not operate.

To rectify this situation, perform one ofthe following fixes:

1. Drive pin L26 with a constant high (logic 1) signal. Thiswill ensure that the fan operates, but will not provide fine grain fan performance control
2. Monitor pin U22 for fan spin information, and then drive pin L26 with an appropriate PWM signal for fan control. This provides the most robust solution for fan performance.
3. Allow pin L26 to be high-Z. This will not interfere with circuit behavior, but does require a special ISE design constraint for pin L26.

For RevD and the RTM version of the KC705 board,a "strong" 1k pulluphas been added for the SM_FAN_PWM control pin to override the bitgen selection of a weak Pulldown. This wouldensure that the only way a customer could turn the fan off is to actively drive the pin and force a selection to a low logic level.

Note: this issue is not expected with the KC705 reference designs that ship with the board. Thisissue is only a possibility with custom designs.

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