AR# 45335

描述

解决方案

The PRBS_ERR_CNT(0/1)_LANE<n> and PRBS_TIMER_(0/1/2)_LANE<n> registers in the Virtex-6 FPGA GTHTransceivers contain theRX pattern checker information like the PRBS error count and time. Virtex-6 FPGA GTH Transceivers User Guide (UG371) Table 4-12 has more information.

Clock domain

The PRBS_TIMER_LANE registers operate off the internal parallel clock of the RX. For example, if the line rate is 10.0 Gbps and the internal width is 16-bit raw mode, thenPRBS_TIMER_LANE runs ona clock of 10Gbps/16 = 625 MHz.

Clearing the registers

The PRBS_ERR_CNT_LANE has a "clear-on-read" option which is enabled by bit 8 of PCS_MISC_CFG0_LANE<n>. If this bit is set to '1', then the error counters will be reset upon read and this also resets the PRBS_TIMER_LANE registers. If only the PRBS_TIMER_LANE registers are read first without reading the PRBS_ERR_CNT_LANE, then the error counter and timer are not cleared even with the self-clear on read mode bit set to '1'.

Order of reading the registers

When reading from these registers, this order must be followed:

PRBS_TIMER_0_LANE, followed by PRBS_TIMER_1_LANE, then followed by PRBS_TIMER_2_LANE to read the full 48 bits out.

Similarly for the error counter, PRBS_ERR_CNT_0_LANE should be read out first followed by PRBS_ERR_CNT_1_LANE to read the full 32 bits out.

链接问答记录

相关答复记录