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  3. AR# 45733: Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.5

AR# 45733

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Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.5

描述

This article contains issues resolved in theVirtex-6 FPGA Integrated Block v2.5 Wrapper for PCI Express that are alsolisted in the readme.txt file that accompanies this version of the core. These are issues that were fixed as part of the update from the previous version of the core.

For other known and resolved issues that may not be in this list see(Xilinx Answer 45723)

解决方案

Resolved Issues

  • CR 612527: m_axis_rx_tuser bits not defined in User Guide
  • CR 612514: m_axis_rx_tuser bits incorrectly referenced in User Guide
  • CR 593920: User Guide incorrectly states legacy interrupts set the Interrupt Status bit
  • CR 615840: Multi-cycle, Non Straddled SOF Scenario is incorrectly shown in User Guide
  • CR 615840: Synplify default constraints invalid

Revision History
01/18/2012 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
45723 Virtex-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface Versions N/A N/A
AR# 45733
日期 05/20/2012
状态 Archive
Type 版本说明
IP
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