AR# 46227

描述

The following answer records cover current known issues as well as commonly asked questions related to MIG 7 series.

NOTE: This answer record is part of the Xilinx MIG 7 Series Solution Center (Xilinx Answer 34243). 

The Xilinx MIG 7 Series Solution Center is available to address all questions related to MIG 7 series.

Whether you are starting a new design with MIG 7 series or troubleshooting a problem, use the MIG 7 Series Solution Center to guide you to the right information.

解决方案

MIG Known Issues
(Xilinx Answer 45195) MIG 7 Series - Release Notes and Known Issues for All ISE Versions
(Xilinx Answer 54025) MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions

MIG Design Advisories
(Xilinx Answer 33566) Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores

MIG 7 Series Top Issues
(Xilinx Answer 50461) MIG 7 Series - Calibration updates in MIG 7 Series v1.6 available with ISE Design Suite 14.2
(Xilinx Answer 47043) MIG 7 Series DDR3/DDR2 - Addition of MMCM to clocking structure starting with v1.5 (available with ISE Design Suite 14.1)
(Xilinx Answer 43344) MIG 7 Series DDR3 - Is Dynamic Calibration supported for DDR3 designs (updated with 14.1 MIG tool release)?
(Xilinx Answer 43879) 7 Series MIG DDR3 - Hardware Debug Guide
(Xilinx Answer 45633) Design Advisory for 7 Series MIG DDR3/DDR2 - Updated pin placement rules for CKE and ODT; existing UCFs must be verified
(Xilinx Answer 40603) MIG 7 Series DDR3/DDR2 - Clocking Guidelines
(Xilinx Answer 41752) MIG 7 Series DDR3/DDR2 - Can an x16 interface fit into a single bank?
(Xilinx Answer 42036) MIG 7 Series- Internal/External Vref Guidelines
(Xilinx Answer 42665) MIG 7 Series - Why does the MIG Example Design fail in BitGen?

Initial ES and General ES Information
(Xilinx Answer 43347) Kintex-7 FPGA Initial Engineering Sample (ES) Master Answer Record and Known Issues
(Xilinx Answer 45696) Kintex-7 FPGA General Engineering Sample (ES) Master Answer Record and Known Issues
(Xilinx Answer 43423) Virtex-7 FPGA Initial Engineering Sample (ES) Known Issues Master Answer Record

链接问答记录

主要问答记录

子答复记录