AR# 47368

描述

This Answer Record deals with issues related to I/O standards in Xilinx devices and aims to increase understanding of Xilinx I/O standards.

This Answer Record is part of the SelectIO Solution Centre (Xilinx Answer 50924)

解决方案

There are different I/O standards developed for different applications.

There are several standard governing bodies such as JEDEC (LVTTL, LVCMOS, HSTL, SSTL etc.), TIA/EIA (LVDS, TMDS, RSDS, LVPECL) and others that create rules and specifications for I/O signaling.

Xilinx FPGAs support many of these I/O standards, which provides the flexibility to have multiple interfaces in a design. 

The device Data Sheet DC and Switching Characteristics contains the requirements for powering the bank and the input and output thresholds.

Details about each kind of I/O in the above are addressed in (Xilinx Answer 47284). 

Each device family has numerous IOSTANDARD settings that can be used.

When applying these I/O settings to a design, there are several rules that should be adhered to as well as settings that need to be properly set. This is discussed in (Xilinx Answer 47278).

When interfacing between any two or more devices, the basic rule is that they should maintain the same/compatible standard(s).

Xilinx devices are flexible enough to interface with most of the devices directly.

However, there are cases where you might need to interface with a 3rd Party device where there is no direct support for the I/O signaling standard.

(Xilinx Answer 47900) discusses the considerations when interfacing between Xilinx FPGA and other devices with respect to I/O standards.

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