AR# 47900

描述

This article forms part of the SelectIO Solution Centre (Xilinx Answer 50924).

It outlines the considerations when interfacing to other devices using SelectIO.

解决方案

For interfacing any two devices, the basic rule is they should have the same or compatible I/O standard(s).

Xilinx devices are flexible enough to interface with most devices directly, due to their large array of IOSTANDARD settings.

Below is a basic checklist for I/O standards interfacing:

• First of all, does the Xilinx Device support the required I/O standard natively?
  If so, examine both datasheets to ensure that they really line up electrically. 
• Do the output logic levels comply with the input logic thresholds in both cases?
  If this is the case then you can proceed with a reasonable amount of confidence.
• If the I/O standard is not supported by Xilinx, is there one available that closely matches? If so, then a close examination of the data sheet is required. 
• Will there need to be level translation? Will you need to AC couple and bias the differential signal to a new common mode voltage?
  If this is the case then Xilinx strongly recommends an IBIS simulation of the proposed scheme to ensure that it is robust at the required data rate.

One common scenario we come across is MIPI-DPHY. 

There is no native support for this in 7 Series devices, so XAPP894 is available.

MIPI-DPHY is supported as an I/O standard in UltraScale+ devices.

For further information on IOSTANDARD settings and attributes see (Xilinx Answer 47278)

Below is a list of important articles relating to interfacing of Xilinx Devices:

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