AR# 47479

描述

解决方案

Introduction

For installation instructions for this release:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm

This file contains release notes for the Xilinx LogiCORE IP Virtex-6 FPGA GTH Transceiver Wizard v1.7 Rev 3 solution. For the latest core updates, see the product page at:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/v6_fpga_gth_transceiver_wizard.html

New Features

ISE Design Suite

• ISE 14.1 software support
• Simplex TX/RX feature support
• Auto-upgrade feature to upgrade from v1.2, v1.3, v1.4, v1.5, v1.6 to v1.7
• Synplify pro scripts for synthesis

Vivado Design Suite

• 2012.1 software support

Supported Devices

ISE Design Suite

The following device families are supported by the core for this release.

• Virtex-6 xc6vhx255t, xc6vhx380t, xc6vhx565t

Vivado Design Suite

The following device families are supported by the core for this release.

• Virtex-6 xc6vhx255t, xc6vhx380t, xc6vhx565t

Resolved Issues

• Fixed CR
  # 584969 - Updated the name of the .xco, .v files and the modulenames to be identical
  # 614187 - RX_BUF_RESET pulse in GTH Reset sequence is too short.
  # 615765 - BUFFER_CONFIG_LANEx must be set to manual adjustment mode based on TX/RX_FABRIC_WIDTH to avoid errors after power-up or configuration
  # 622772 - Default value of PMA_LPBK_CTRL_LANEx needs to be updated to 'h0002
  # 621026 - Attribute DFE_TRAIN_CTRL_LANEx needs to brought out to mgt wrapper
  # 622397 - Connect RXBUFRESET of lanes 1/2/3 to rxbufreset when GTHX4LANE = 1
  # 641880 - Lane powerdown can cause burst of errors in the Quad. Updated the default value of attribute RX_P1_CTRL.

Known Issues

The following are known issues for v1.7 of this core at time of release:

• Limited hardware testing was done for the Virtex-6 GTH Wizard on ML627 board
• Attribute and port settings for OTU-4 are applicable to single lane only. User has to integrate other OTU-4 compatible logic manually intheir design
• For 16 and 20 bit datapath widths, multiple line rates and multiple datapath widths cannot be selected across multiple lanes

The most recent information, including known issues, work-arounds, and resolutions for this version is provided in the IP Release Notes Guide located at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf

Technical Support

To obtain technical support, create a WebCase. Questions are routed to a team with expertise using this product.

Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.

Other Information

This version of the wizard supports CES silicon only. Using a wrapper generated with this version of the wizard to program a Production Virtex-6 HXT device isnot recommended or supported. Use v1.8 or later to program Production devices. Please refer to (Xilinx Answer 41464) for guidance on how to distinguish Production from ES devices and for additional details.

Core Release History

Date By Version Description
================================================================================
04/24/2012 Xilinx, Inc. 1.11 ISE 14.1 and Vivado 2012.1 support
10/19/2011 Xilinx, Inc. 1.7(Rev3) ISE 14.1 and Vivado 2012.1 support
01/18/2012 Xilinx, Inc. 1.10 ISE 13.4 support
10/19/2011 Xilinx, Inc. 1.9 ISE 13.3 support
10/19/2011 Xilinx, Inc. 1.7(Rev2) ISE 13.3 support
06/22/2011 Xilinx, Inc. 1.8(Rev1)ISE 13.2 support
04/08/2011 Xilinx, Inc. 1.8(Rev0) ISE 13.1 support
04/08/2011 Xilinx, Inc. 1.7(Rev1)ISE 13.1 support
03/01/2011 Xilinx, Inc. 1.7 ISE 13.1 support
12/14/2010 Xilinx, Inc. 1.6 ISE 12.4 support
09/21/2010 Xilinx, Inc. 1.5 ISE 12.3 support
07/23/2010 Xilinx, Inc. 1.4 ISE 12.2 support
04/19/2010 Xilinx, Inc. 1.3 ISE 12.1 support
12/02/2009 Xilinx, Inc. 1.2 ISE 11.4 support
09/16/2009 Xilinx, Inc. 1.1 Initial release
================================================================================

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